Digital phase discrimination based on frequency sampling

ABSTRACT

The present invention, generally speaking, provides a simple, all-digital method and apparatus for determining the phase of a first clock signal relative to a second clock signal. The first clock signal may be a digital approximation of a periodic analog signal such as an RF signal. A sampling technique is employed that produces a stream of digital bits containing relative phase information. From the stream of digital bits is formed a digital word indicative of the relative phase. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to digital phase discrimination.

[0003] 2. State of the Art

[0004] Phase discrimination is important in digital radiocommunications, in particular in any angle modulation digital radioreceiver. Phase discrimination and frequency discrimination are closelyrelated. Frequency discrimination is typically performed using analogcircuitry, e.g. an IQ frequency discriminator. Analog frequencydiscriminators have substantial drawbacks. In the case of an IQfrequency discriminator, the discriminator requires a number of analogcomponents, two A/D conversions and a numerical arctangent operation,rendering the circuit quite complex.

[0005] Known methods exist for producing a value representing theinstantaneous phase of a signal using only digital logic elements.Various such methods are described in U.S. Pat. No. 5,084,669,incorporated herein by reference. In particular, the foregoing patentdescribes a digital circuit for determining the instantaneous phase of asignal, from which the instantaneous frequency may be obtained ifdesired. Although the implementation of the circuit is all digital, itis quite involved. An improved method and apparatus for determining in asimple, all-digital manner the instantaneous phase of a signal wouldtherefore likely be well-received by those skilled in the art.

SUMMARY OF THE INVENTION

[0006] The present invention, generally speaking, provides a simple,all-digital method and apparatus for determining the phase of a firstclock signal relative to a second clock signal. The first clock signalmay be a digital approximation of a periodic analog signal such as an RFsignal. A sampling technique is employed that produces a stream ofdigital bits containing relative phase information. From the stream ofdigital bits is formed a digital word indicative of the relative phase.The digital word may be formed using a digital filter. Advantageously,an extensive body of digital filtering techniques applicable toSigma-Delta (sometimes referred to as Delta-Sigma) A ID converters maybe applied directly to the digital stream. By using anappropriately-chosen weighting function, high accuracy may be obtained.

BRIEF DESCRIPTION OF THE DRAWING

[0007] The present invention may be further understood from thefollowing description in conjunction with the appended drawing. In thedrawing:

[0008]FIG. 1 is a block diagram illustrating a sampled-data model of aSigma-Delta modulator and of a sampling circuit applied to frequencysampling in accordance with one embodiment of the present invention;

[0009]FIG. 2 is a table helpful in explaining operation of the circuitmodel of FIG. 1 in the instance of an input frequency that is 0.6875times a reference frequency;

[0010]FIG. 3 is a timing diagram illustrating the principle of operationof the circuit model of FIG. 1 as applied to frequency sampling;

[0011]FIG. 4 is a schematic diagram of one example of a frequencysampling circuit described by the circuit model of FIG. 1;

[0012]FIG. 5 is a first timing diagram illustrating operation of thefrequency sampling circuit of FIG. 4;

[0013]FIG. 6 is a second timing diagram illustrating operation of thefrequency sampling circuit of FIG. 4;

[0014]FIG. 7 is a graph of two alternative weighting functions that maybe used to perform digital filtering of a digital bit stream produced bya circuit such as that of FIG. 4;

[0015]FIG. 8 is a graph illustrating the accuracy obtained from adigital frequency discriminator using a constant weighting function;

[0016]FIG. 9 is a graph illustrating the accuracy obtained from adigital frequency discriminator using a triangular weighting function;and

[0017]FIG. 10 is a block diagram of one example of a digital filter thatmay be used in conjunction with a frequency sampling circuit such asthat of FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The approach followed by the digital frequency discriminator ofthe present invention may be appreciated by analogy to Sigma-Delta A/Dconversion, well-documented in the prior art by such references as“Oversampling Delta-Sigma Data Converters”, Candy, et al., IEEE Press,pages 1-6, Piscataway, N.J. (1992). A Sigma-Delta converter modulates avarying-amplitude analog input signal into a simple digital code at afrequency much higher than the Nyquist rate. The design of the modulatorallows resolution in time to be traded for resolution in amplitude. Asampled-data circuit model of a Sigma-Delta modulator, shown in FIG. 1,may be directly applied to frequency sampling as described herein.

[0019] Referring to FIG. 1, an input signal x_(i) occurring at sampletime i has subtracted from it the output signal y_(i) at sample time i.The result is applied to an accumulator having an output signal w_(i.) A“new” input signal of the accumulator at sample time i is combined withthe “old” output signal of the accumulator to form a new output signalof the accumulator. The output signal of the accumulator is quantized,the quantization being represented as the addition of an error e_(i).The output signal of the quantizer is the final output signal y_(i).

[0020] Assume now that x_(i) is the ratio of two frequencies and thatthe quantizer is a two-level quantizer. Further assume that the ratio ofthe two frequencies for the time period in question is, say, 0.6875. Asshown in FIG. 2, the latter value is accumulated a first time, giving anaccumulated value of 0.6875. This valuing being less than 1, the value0.6875 is again added to the accumulated value, giving a new accumulatedvalue of 1.375. Since this value is now greater than 1, 1 is subtractedfrom 0.6875 and the result (0.6875−1=−0.3125) added to the accumulatorto give a value of 1.0625. Operation proceeds in this fashion. Duringthe foregoing sequence of operations, a data stream is produced bytaking the integer portion, 1 or 0, of each accumulated value.

[0021] Referring to FIG. 3, the interpretation of the sequence ofnumbers shown in FIG. 2 may be appreciated. Two clock signals are shown.Again, it is assumed that the ratio of the frequency of the upper clocksignal to that of the lower clock signal during the period of interestis 0.6875. At time t=0, rising edges of both clock signals coincide. Atthe first subsequent rising edge of the lower clock signal, 0.6875periods of the upper clock signal have elapsed. At the next rising edgeof the lower clock signal, 1.375 periods of the upper clock signal haveelapsed. At the next rising edge of the lower clock signal, 1.0625periods of the upper clock signal have elapsed since the elapse of thefirst period of the upper clock signal, and so on.

[0022] A schematic diagram of a capture circuit, or frequency samplingcircuit, that may be used to data samples corresponding to the datastream described in the foregoing example is shown in FIG. 4. In theillustrated embodiment, it is assumed that the ratio of the clocksignals is such that no more than one rising edge of the faster clockwill occur during a single period of the slower clock. In otherembodiments, this assumption need not apply.

[0023] The capture circuit includes a input portion 401 and an outputportion 403. The input portion includes two sections Ch1 and Ch2 thatmust be carefully matched to minimize errors. Each section comprises achain of two or more D flip-flops coupled in series. In the followingdescription, the same reference numerals will be used to reference therespective flip-flops themselves and their respective output signals.

[0024] Within each section, the first flip-flop in the chain is clockedby a sampled clock signal Fx. The succeeding flip-flops in the chain areclocked by a sampling clock signal Fs. The D input of the firstflip-flop Q1 in the upper section is coupled to the {overscore (Q)}output of the same. The D input of the first flip-flop in the lowersection is coupled to the Q output of the first flip-flop in the uppersection. The remaining flip-flops in both sections are coupled inseries—i.e., Q to D, Q to D.

[0025] The function of the input portion is to 1) produce two signals,logical inverses of one another, that transition on rising edges of theclock signal Fx; 2) to latch the values of the two signals on the risingedge of the clock signal Fs; and 3) to detect transitions from one clockto the next. Additional intermediate stages in series with Q3 and Q4 maybe required to minimize metastability resulting from the asynchrony ofthe two clock signals, and in fact multiple such stages may be desirablein a particular design.

[0026] The output portions include, in an exemplary embodiment, threetwo-input NAND gates. Respective NAND gates N1 and N2 are coupled to theD and {overscore (Q)} signal of the final flip-flop stages of the inputsections. Output signals of the NAND gates N1 and N2 are combined in thefurther NAND gate N3 to form the final output of the capture circuit.

[0027] The function of the output portion is to detect a change in theinput clock signal level from one sample clock to the next in either oftwo channels formed by the two input sections. The two input sectionsfunction in a ping-pong fashion, alternately detecting changes in theinput clock signal level.

[0028] Operation of the capture circuit of FIG. 4 may be more fullyappreciated with reference to the timing diagram of FIG. 5. The firststages of the two channels form inverse signals Q1 and Q2 approximatelycoincident with (but slightly delayed from) rising edges of the inputclock signal. The signals Q3 and Q4 are formed by sampling the signalsQ1 and Q2, respectively, in accordance with the sample clock. Thesignals Q5 and Q6, respectively, are delayed replicas of the signals Q3and Q4. The NAND gates together realize the logic functionX=Q3·{overscore (Q5)} v Q4·{overscore (Q6)}.

[0029] In the example of FIG. 5, the illustrated signals are allidealized square-wave signals. In actuality, the signals will havefinite rise and fall times. The possible effect of the finite rise andfall times of the signals Q1 and Q2 and the asynchrony of the circuit ismetastability, as illustrated in FIG. 6. Here, the signals Q3 and Q5 andthe signals Q4 and Q6 are each in an indeterminate state for one cycle.The resulting output of the circuit may or may not be correct. However,because the decision was a “close call” to begin with, the effect of anoccasional erroneous decision on the overall operation of the circuit isnegligible. The time window of instability is reduced by increasing theoverall gain in the path. If the gain in Q3 and Q9 is sufficient toreduce the probability of an error to an acceptable level, then noadditional circuitry is required. If not, then additional circuitry willbe required to increase the gain.

[0030] In order to recover the ratio of the frequencies of the two clocksignals from the data stream produced by a capture circuit such as theone of FIG. 4, digital filtering is applied. Advantageously, anextensive body of digital filtering techniques applicable to Sigma-Delta(or Delta-Sigma) A/D converters may be applied directly to the digitalstream. Furthermore, by using an appropriately-chosen weightingfunction, high accuracy may be obtained.

[0031] The weighted sum of products is an example of an FIR filter. Theweighting function described heretofore is therefore that of an FIRfilter in digital filtering theory. It should be recognized, however,that IIR filters can also be used. In the process of FIR digitalfiltering, the weighting function is applied to a “window” of datasamples to obtain an estimate of the ratio of frequencies in the centerof the window. The window is then “picked up and moved” to the nextsequence of samples. Windowing will typically overlap. A window mayinclude 256 samples, for example.

[0032] Referring to FIG. 7, two alternative weighting functions areshown for a window of 256 samples. The weighting functions arenormalized, meaning that the area under the weighting function is unity.One weighting function, indicated in dashed lines, is a straight-line,constant weighting function. Another weighting function, indicated insolid line, is a triangular weighting function. The weighting functionis the impulse response function in digital filters.

[0033] Results of digital filtering using the straight-line weightingfunction and the triangular weighting function respectively, are shownin FIG. 8 and FIG. 9. In the case of both FIG. 8 and FIG. 9, thefrequency ratio was increased from just under 0.687 to just over 0.693.As seen in FIG. 8, using a straight-line weighting function, thequantized signal oscillates between two levels that are adjacent to theinput in such a manner that its local average equals the average input.The average error was calculated to be 1772 ppm. As seen in FIG. 9,using a triangular weighting function, the quantized signal tracks theinput with an average error of 83 ppm.

[0034] A schematic diagram of an exemplary frequency accumulator thatapplies a triangular weighting function and that may be used toaccomplish the desired digital filtering is shown in FIG. 10. In theexample shown, the frequency accumulator uses a 7-bit counter 101, a14-bit adder 103 and a 14-bit register 105. The 7-bit counter is clockedby the sample frequency Fs. The output of the 7-bit counter is providedto one input of the adder. The function of the 7-bit counter is to countup from 0 to 127 and then down from 127 to 0. The count of 127 occurstwice in succession. This behavior is achieved using a flip-flop 107.The flip-flop is clocked by the sample frequency Fs. A Terminal Countsignal of the 7-bit adder is input to the flip-flop. The output of theflip-flop is coupled to a Count Down input of the 7-bit counter.

[0035] The “oversampled” data stream is coupled to a control input ofthe adder. When the current bit of the data stream is a 1, an additionis performed. When the current bit is a 0, no addition is performed. ACarry In input of the adder is tied high, effectively causing the rangeof weights to be 1 to 128.

[0036] The 14-bit register is clocked by the sample frequency Fs. Itsoutput is applied to the other input of the adder. Its input receivesthe output word produced by the adder. The function of the 14-bit adderis to perform an accumulation operation for 256 clocks. At theconclusion of the 256 clocks, the output of the 14-bit adder is used asan estimator for the frequency ratio. More particularly, in the exampleshown, the output of the accumulator is equal to R×128×129, where R isthe frequency ratio estimator.

[0037] The foregoing technique may be readily extended to phasediscrimination. Various different methods and apparatus for digitalphase discrimination will be described entailing different designtradeoffs.

[0038] The first method is conceptually straightforward butcomputationally expensive. Referring to FIG. 11A, the same observedfrequency data stream and the same set of weights corresponding to atriangular weighting function (FIG. 11B) are used. The ratio of thereference frequency to the sampled frequency over a relatively longperiod of time is first determined using the technique describedpreviously. Having obtained this frequency ratio estimator, short-termfrequency deviations are estimated by calculating the same frequencyestimate as before but at a relatively high rate, as often as once persample period. That is, successive samples are all taken using thecircuit of FIG. 10, as often as each sample period. The difference (ΔF)of each frequency estimate (F) from the previously-determined frequencyratio (Fr) is calculated, multiplied by an appropriate scale factor kand accumulated to obtain a corresponding phase estimate Pf. (The firstvalue of Pf is an arbitrarily chosen initial condition, chosen forcomparison to an ideal estimate. In practice, the phase may beinitialized to a value based on a priori knowledge of signalcharacteristics, or, absent such a priori knowledge, may be set to zeroupon detection of a phase inflection point.)

[0039] A phase-plot simulation comparing actual phase of a specifiedwaveform (solid-line) with estimated phase using the foregoing phaseestimation method (dashed-line) is shown in FIG. 11C.

[0040] The foregoing “frequency difference” phase estimation method iscomputationally expensive because of the need to calculate frequencyestimates at a relatively high rate. A “pre-summation difference” phaseestimation method obviates this requirement. Referring to FIG. 12A,instead of subtracting the frequency ratio from a frequency estimate,the frequency ratio Fr is subtracted from the sampled data streamitself. Assuming that the data stream is a bit stream of ones and zerosonly, and assuming a frequency ratio Fr=0.6875, then the pre-summationdifference Y will have one of only two values, Y=1−0.6875=0.3125 orY=0−0.6875=−0.6875. The Y values are accumulated to obtain correspondingvalues PX. Phase estimates PP_(n) are obtained by filtering the PXvalues in substantially the same manner as described previously inrelation to forming frequency estimates (using the identical weightingfunction, FIG. 12B, for example) with the exception that the filteredvalues are scaled by the scale-factor k.

[0041] The pre-summation difference phase-calculation may be shown to bemathematically equivalent to the frequency difference phase calculation.Simulation results, shown in FIG. 12C, are therefore the same as in FIG.11C. The hardware realization, however, may be considerably simplerusing the pre-summation difference phase calculation, since only onecomputation is required per phase point. Such a hardware realization isshown in FIG. 13.

[0042] The pre-summation difference phase estimator of FIG. 13 includesgenerally a first accumulator ACC1, a weight generator WG similar oridentical to the weight generator previously described in relation toFIG. 10, and a second accumulator ACC2.

[0043] The accumulator ACC1 functions to produce phase numbers PX_(i) incorrespondence to bits (or in other embodiments, symbols) of theobserved frequency data stream and includes a multiplexer 1301, an adder1303 and a register (e.g., a 16-bit register) 1305. The multiplexer 1301selects one of the two possible values of Y_(i) in accordance with thevalue of X and applies Y_(i) to the adder 1303. The register value isadded to Y_(i) to form PX_(i), which is then strobed into the register.The adder 1303 and register 1305 therefore accumulate the PX_(i) values.

[0044] The PX_(i) values are then filtered in the accumulator ACC2,which includes a multiplier 1307, an adder 1309 and a register 1311. Themultiplier receives weights from the weight generator WG and PX_(i)values from the accumulator ACC1. Respective weights and PX_(i) valuesare multiplied and the products accumulated, e.g., for 128 clock cycles,to produce a phase estimator PP. The multiplier may be constructed so asto apply the scale factor k to each product during the accumulationprocess.

[0045] An even simpler realization may be achieved using an integerdifference phase calculation. The integer difference phase calculationis not mathematically equivalent to the foregoing methods, but is veryclose. Referring to FIG. 14A, this method uses, in addition to theobserved frequency data stream, a reference frequency data stream thatwould result if the reference frequency were applied to the capturecircuit of FIG. 4 (with the same clock). A running sum D_(i) is thenformed of the integer difference X_(i)−R_(i). In many practicalapplications, such as the one illustrated in FIGS. 14 and 15, Di willhave the values 1, 0 and −1 exclusively. The general case in which D_(i)takes on other values may be appreciated and understood, however, fromthe present example, and is embraced by the present description.

[0046] Phase estimates are formed by filtering the D_(i) values in thesame or similar manner as previously described. The same triangularweighting function may be used FIG. 14B. The integer difference phasecalculation method produces identical simulation results, FIG. 14C, asthe preceding methods.

[0047] Referring to FIG. 15, in the instance where D takes on the values1, 0 and −1 exclusively, the corresponding hardware realization may besubstantially simplified (as compared to that of FIG. 13, for example).

[0048] The integer difference phase estimator of FIG. 15, like that ofFIG. 13, includes generally a first accumulator ACC1, a weight generatorWG, and a second accumulator ACC2. The accumulator ACC1 is ofconsiderably different construction than the corresponding structure ofFIG. 13. The accumulator ACC1 of FIG. 15 includes a reference patterngenerator 1501, a 1-bit subtractor 1503, a 2-bit adder 1505 and a 2-bitregister 1507. The 1-bit subtractor subtracts respective R values fromrespective X values. The 2-bit adder and the register accumulate theresulting D_(i) values which, as explained previously, may beconstrained to 1, 0, −1 only.

[0049] The weight generator WG and the accumulator ACC2 aresubstantially the same as in FIG. 13, described previously. However,because D_(i) takes on the values 1, 0 and −1 exclusively, no multiplieris required. Instead, if D_(i)=1, the weight value is added to theaccumulated value, and if D_(i)=−1, the weight value is subtracted. (IfD_(i)=0, the accumulated value remains unchanged.) The savings of ahardware multiplier is a particular advantage of the implementation ofFIG. 15.

[0050] A further method of phase estimation is referred to as the clockmeasure phase calculation method. Referring to FIG. 16A, this method issimilar to the previous integer difference phase calculation methodinsofar as R, X and D are concerned. This method, however, uses inaddition to the reference frequency data stream R, “clock measure”numbers RG, which are the same as the numbers appearing in FIG. 2.Moreover, the weight function used is distinctly different, as shown inFIG. 16B. Clock measure phase estimate values PC are obtained using thefollowing formula:

PC _(n) =k·(D _(n) −frac(RG _(n))+0.5 +Σ_(i)(w _(i) ·X _(i+n−Γ)))

[0051] Simulation results using the clock measure phase calculationmethod are shown in FIG. 16C.

[0052] Referring to FIG. 17, the clock measure phase estimator includesgenerally a first accumulator ACC1, a weight generator WG, and a secondaccumulator ACC2. The estimator additionally includes a summation block1701.

[0053] The accumulator block ACC1 is substantially the same as theaccumulator block ACC1 of FIG. 15. Note, however, that the referencepattern generator generates both the reference frequency data stream R,used within the accumulator ACC1, and the clock measure data stream RGwhich is input to the summation block 1701.

[0054] The weight generator includes a counter 1703 and weight generatorlogic 1705.

[0055] The accumulator ACC2 includes an adder 1707 and a register 1709.When X=1, the weight value from the weight generator is added to thecontents of the register 1709. The output of the adder becomes the newinput of the register, which performs an accumulator operation for,e.g., 128 clock cycles.

[0056] At the conclusion of the accumulation operation of ACC2, theoutputs of ACC1 and ACC2, together with the corresponding RG value, aresummed in the summation block 1701.

[0057] It will be appreciated by those of ordinary skill in the art thatthe invention can be embodied in other specific forms without departingfrom the spirit or essential character thereof. The presently disclosedembodiments are therefore considered in all respects to be illustrativeand not restrictive. The scope of the invention is indicated by theappended claims rather than the foregoing description, and all changeswhich come within the meaning and range of equivalents thereof areintended to be embraced therein.

What is claimed:
 1. An apparatus for generating delta/sigma modulationquantized data representing the ratio of two frequencies Fx and Fs,comprising: a counter circuit for counting the number of clock edges ofFs occurring in the time period between clock edges of Fx; and aregister circuit for storing the value of the counter circuit at eachclock edge of Fs; the sequence of values from the register circuitconstituting the delta/sigma modulation quantized data.